The present invention relates to an output buffer circuit.
FIG. 14 is a circuit diagram showing the operating principles of a conventional output buffer circuit with slew-rate controlling capability. As shown, high output transistors QP21 through QP24 and low output transistors QN21 through QN24 are provided in four stages between an input terminal 91 and an output terminal 92. Sources of the high output transistors QP21 through QP24 are all connected to the power supply. Their drains are connected to drains of the low output transistors QN21 through QN24, respectively, and in common to the output terminal 92. Sources of the low output transistors QN21 through QN24 are all grounded.
An input signal IN received from the input terminal 91 is applied to a gate of the high output transistor QP21 and delay circuits 111 and 121. Delay circuits 111 through 113 are connected in series and delay circuits 121 through 123 are connected in series. Each delay circuit delay the input signal IN by a predetermined time interval.
Output signals from the delay circuits 111, 112, and 113 are applied to gates of the high output transistors QP22, QP23, and QP24, respectively.
Output signals from the delay circuits 121, 122, and 123 are applied to gates of the low output transistors QN22, QN23, and QN24, respectively.
In this circuit configuration, the delay circuits 111 through 113 cause a time lag among the high output transistors QP21 through QP24 so that the input signal IN is sequentially applied to the gates of the transistors QP21 through QP24 in this order. Also, the delay circuits 121, 122, and 123 cause a time lag among the low output transistors QN21 through QN24 so that the input signal IN is sequentially applied to the gates of the transistors QN21 through QN24 in this order.
When the input signal IN makes a HIGH to LOW or LOW to HIGH transition, the high output transistors QP21 through QP24 or the low output transistors QN21 through QN24 are turned on in sequence after a time lag. Thus, slew rate of an output signal OUT during periods of relatively heavy load on the output terminal 92 is brought close to that during periods of relatively light load on the output terminal 92.
By raising the slew rate during periods of relatively heavy load on the output terminal 92, the conventional output buffer circuit has relieved a difference in the slew rate of the output signal OUT due to changes of the load on the output terminal 92.
However, even if the transistor characteristics change according to load capacity of the output terminal 92 or ambient temperature, the delay circuits 111 through 113 and the delay circuits 121 through 123 cause a constant time lag among the high output transistors QP21 through QP24 and the low output transistors QN21 through QN24, respectively. Therefore, the conventional output buffer circuit in FIG. 14 has been posing a problem of the occurrence of variations in the slew rate of output waveforms of the output signal OUT due to changes of the load on the output terminal 92, as indicated by P1 through P4 in FIG. 4.
Another problem is high current consumption. That is, even if the load on the output terminal 92 is light enough to achieve good slew rate only with a single inverter, the conventional output buffer circuit turns on the four transistors in sequence, which is equivalent to driving four inverters in sequence. This requires extra current.
A first aspect of the present invention is directed to an output buffer circuit comprising: an input terminal receiving an input signal; an output terminal outputting an output signal; a delay circuit for delaying the input signal by a delay time to output a delay signal, the delay time varying according to a potential of the output signal; and an output buffer portion for outputting the output signal in response to a relative input signal correlated with the input signal, the output buffer portion receiving a relative delay signal correlated with the delay signal, a driving capability of the output buffer portion to the relative input signal varying according to the delay time.
According to a second aspect of the present invention, in the output buffer circuit of the first aspect, the delay time includes a plurality of delay times; the delay signal includes a plurality of delay signals obtained by delaying the input signal by the plurality of delay times; the output buffer portion includes a plurality of buffer portions provided in a one-to-one correspondence with the plurality of delay signals, for outputting the output signal in response to the plurality of delay signals; and the relative input signal and the relative delay signal are the same signal including the plurality of delay signals.
According to a third aspect of the present invention, in the output buffer circuit of the first aspect, the relative input signal includes the input signal, the output buffer circuit further comprising: a plurality of data storage portions for storing control data, each receiving the delay signal at a different input time that elapses from a logic level transition on the input signal, and if the delay signal makes the logic level transition, setting the control data to indicate a halt in the operation of the output buffer, wherein the relative delay signal includes the control data in the plurality of data storage portions; wherein the output buffer portion includes a plurality of buffer portions provided in a one-to-one correspondence with the plurality of data storage portions, the operating/halting status of each of the plurality of output buffer portions being determined on the basis of the control data stored in a corresponding data storage portion.
According to a fourth aspect of the present invention, in the output buffer circuit of the first aspect, the input signal has first and second logic levels; and the output buffer portion includes a first logic output portion for setting the output signal to the first logic level under operating conditions on the basis of the relative delay signal, and a second logic output portion for setting the output signal to the second logic level under operating conditions on the basis of the relative delay signal. The output buffer circuit further comprises: a first logic output control portion for bringing the first logic output portion into operation when the input signal makes a first transition from the second logic level to the first logic level; and a second logic output control portion for bringing the second logic output portion into operation when the input signal makes a second transition from the first logic level to the second logic level.
According to a fifth aspect of the present invention, the output buffer circuit of the third aspect further comprises an input time setting portion for setting the input time of each of the plurality of data storage portions on the basis of a plurality of RC delay signals obtained by delaying the input signal with RC time constant.
According to a sixth aspect of the present invention, the output buffer circuit of the third aspect further comprises an output buffer starting portion for activating the output buffer portion at a time when a predetermined condition is satisfied, by setting the control data in the plurality of storage portions to indicate the operation of the output buffer.
According to a seventh aspect of the present invention, in the output buffer circuit of the sixth aspect, the time when the predetermined condition is satisfied includes a time of power-on and a time of reset.
According to an eighth aspect of the present invention, in the output buffer circuit of the sixth aspect, the output buffer starting portion has a timer function, for monitoring a state of the output signal at predetermined time intervals and activating the output buffer portion at a time when the state of the output signal does not satisfy a predetermined criterion, as the time when the predetermined condition is satisfied.
According to a ninth aspect of the present invention, in the output buffer circuit of the sixth aspect, the output buffer starting portion includes an output potential monitoring portion for performing logical operation on the basis of the potential of the output signal, and monitoring the potential of the output signal all the time on the basis of the result of the logical operation; and the time when the predetermined condition is satisfied includes a time when the potential of the output signal does not satisfy a predetermined criterion according to the result of the logical operation.
In the output buffer circuit according to the first aspect, the driving capability of the output buffer portion to the relative input signal varies according to the delay time and the delay time varies according to the potential of the output signal.
The potential of the output signal and the delay time can thus be correlated so that the driving capability of the output buffer portion is improved when the load on the output terminal is relatively heavy and is impaired when the load is relatively light on the basis of the potential of the output signal. This allows the slew rate of the output waveforms of the output signal to be maintained within a predetermined range regardless of changes of the load on the output terminal.
In the output buffer circuit according to the second aspect, the plurality of output buffer portions output the output signal in response to the plurality of delay signals obtained by delaying the input signal by the plurality of delay times, respectively. Thus, starting times for the operation of the plurality of output buffer portions in response to the input signal are delayed by a plurality of delay times, respectively.
The potential of the output signal and the plurality of delay times can thus be correlated so that the plurality of delay times are shortened when the load on the output terminal is relatively heavy and are lengthened when the load is relatively light on the basis of the potential of the output signal. Further, the driving capability of the plurality of output buffer portions can be improved when the load is relatively heavy by speeding up the starting times for the operation of the plurality of output buffer portions and can be impaired when the load is relatively light by delaying the starting times. This allows the slew rate of the output waveforms of the output signal to be maintained within a predetermined range regardless of changes of the load on the output terminal.
In the output buffer circuit according to the third aspect, the operating/stopping status of each of the plurality of output buffer portions is determined on the basis of the control data in the corresponding data storage portion.
Therefore, after the control data in the plurality of data storage portions is set to effect the operation of the plurality of output buffer portions, the potential of the output signal and the delay times can be correlated so that the delay times are lengthened when the load on the output terminal is relatively heavy and are shortened when the load is relatively light on the basis of the potential of the output signal. Further, the driving capability of the plurality of output buffer portions can be improved when the load is relatively heavy by reducing the rate of the control data which indicates a halt in the operation of the plurality of output buffer portions, in the plurality of data storage portions, and can be impaired when the load is relatively light by increasing the rate of the control data which indicates the operation of the plurality of output buffer portions. This allows the slew rate of the output waveforms of the output signal to be maintained within a predetermined range regardless of changes of the load on the output terminal.
In the output buffer circuit according to the fourth aspect, the first logic output control portion brings the first logic output portion into operation when the input signal makes the first transition, and the second logic output control portion brings the second logic output portion into operation when the input signal makes the second transition. This achieves efficient utilization of only a necessary logic output portion among the first and second logic output portions.
In the output buffer circuit according to the fifth aspect, the input time setting portion sets the input times of the plurality of data storage portions on the basis of the plurality of RC delay signals obtained by delaying the input signal with RC time constant. This allows setting of accurate input times.
In the output buffer circuit according to the sixth aspect, the output buffer starting portion activates the output buffer portions at a time when a predetermined condition is satisfied. This ensures stability in the output signal.
In the output buffer circuit according to the seventh aspect, the output buffer portions are activated at power-on and reset. This ensures stability in the output signal.
In the output buffer circuit according to the eighth aspect, the output buffer starting portion monitors the status of the output signal at predetermined time intervals and activates the output buffer portions at a time when the status of the monitored output signal does not satisfy a predetermined criterion. This ensures stability in the output signal.
In the output buffer circuit according to the ninth aspect, the output buffer starting portion activates the output buffer portions at a time when the potential of the output signal does not satisfy a predetermined criterion according to the result of the logical operation. This ensures stability in the output signal.
Further, the output potential monitoring portion may be configured as a logic circuit for performing the above logical operation. This simplifies the circuit configuration.
An object of the present invention is to provide an output buffer circuit that maintains the slew rate of the output waveforms of the output signal within a predetermined range regardless of changes of the load on the output terminal.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.